View HM6288SERIES_198334.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM6288 Series
16384-word x 4-bit High Speed CMOS Static RAM
Description
The Hitachi HM6288 is a high speed 64k static RAM organized as 16-kword x 4-bit. It realizes high speed access time (25/35 ns) and low power consumption, using CMOS process technology. It is most advantageous for the field where high speed and high density memory is required, such as cache memory for mainframes or 32-bit MPUs. The HM6288, packaged in a 300-mil plastic DIP and SOJ, is available for high density mounting. A low power version retains data with battery backup.
Features
* Single 5 V supply arid high density plastic package * High speed: fast access time 25/35 ns (max) * Low power dissipation: Active mode 300 mW (typ) Standby mode 100 W (typ) * Completely static memory No clock or timing strobe required * Equal access and cycle times. * Directly TTL compatible all inputs and outputs
HM6288 Series
Ordering lnformation
Type No. HM6288P-25 HM6288P-35 HM6288LP-25 HM6288LP-35 HM6288JP25 HM6288JP-35 HM6288LJP-25 HM6288LJP-35 Access Time 25 ns 35 ns 25 ns 35 ns 25 ns 35 ns 25 ns 35 ns 300-mil, 24-pin SOJ (CP-24D) Package 300-mil, 22-pin plastic DIP (DP-22NB)
Pin Arrangement
HM6288P Series A0 A1 A2 A3 A4 A5 A6 A7 A8 CS VSS 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC A13 A12 A11 A10 A9 I/O1 I/O2 I/O3 I/O4 WE A0 A1 A2 A3 A4 A5 A6 A7 A8 CS NC VSS HM6288JP Series 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A13 A12 A11 A10 A9 NC I/O1 I/O2 I/O3 I/O4 WE
(Top view)
(Top view)
Pin Description
Pin Name A0-A13 I/O1-I/O4 CS WE VCC VSS Function Address lnput/output Chip select Write enable Power supply Ground
2
HM6288 Series
Block Diagram
A0 A1 A2 A3 A4 A5 A6 I/O1 I/O2 I/O3 I/O4 Input data control A7 CS WE
Row decoder
Memory array 128 rows 512 columns
VCC VSS
Column I/O Column decoder
A13
Truth Table
CS H L L WE x H L Mode Standby Read Write VCC Current I SB , I SB1 I CC I CC I/O Pin High-Z Dout Din Ref. Cycle -- Read cycle 1, 2 Write cycle 1, 2
Note: x: Don't care.
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Temperature under bias Symbol VT PT Topr Tstg Tbias Value -0.5 to +7.0 1.0 0 to +70 -55 to +125 -10 to +85
*
Unit V W C C C
Note: VT min.: -2.0 V for pulse width 10 ns
3
HM6288 Series
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5
*1
Typ 5.0 0 -- --
Max 5.5 0 6.0 0.8
Unit V V V V
1. VIL min.: -2.0 V for pulse width 10 ns
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
Parameter Input leakage current Output leakage current Operating power supply current Standby V CC current Standby V CC current 1 Symbol |ILI| |ILO | I CC I SB I SB1 Min -- -- -- -- -- Typ* 1 Max -- -- 60 15 0.02 2.0 2.0 120 30 2.0 Unit A A mA mA mA Test conditions VCC = Max, Vin = VSS to V CC CS = VIH, VI/O = VSS to V CC CS = VIL, II/O = 0 mA, min. cycle CS = VIH, min. cycle CS V CC - 0.2V, 0 V Vin 0.2V or VCC - 0.2V Vin
I SB1*2 Output low voltage Output high voltage VOL VOH
-- -- 2.4
0.02 -- --
0.1 0.4 --
mA V V I OL = 8 mA I OH = -4.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. L-version
Capacitance (Ta = 25C, f = 1.0 MHz)*1
Parameter Input capacitance lnput/output capacitance Note: Symbol Cin CI/O Min -- -- Max 6 8 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V
1. This parameter is sampled and not 100% tested.
4
HM6288 Series
AC Characteristics
Test Conditions * * * * Input pulse levels: 0 V to 3.0 V Input and output timing reference levels: 1.5 V Input rise and fall time: 5 ns Output load: See figure
+5V 480 Dout 255 Dout 255 +5V 480
30 pF *1
5 pF *1
Output load (A)
Output load (B) (for tHZ, tLZ, tWZ, and tOW )
Note: 1. Including scope and jig.
Read Cycle
HM6288-25 Parameter Read cycle time Address access time Chip select access time Output hold from address change Chip selection to output in low-Z Chip deselection to output in high-Z Chip selection to power up time Chip deselection to power down time Note: Symbol t RC t AA t ACS t OH t LZ
*1 *1
HM6288-35 Min 35 -- -- 5 5 0 0 -- Max -- 35 35 -- -- 20 -- 30 Unit ns ns ns ns ns ns ns ns
Min 25 -- -- 3 5 0 0 --
Max -- 25 25 -- -- 12 -- 25
t HZ t PU t PD
1. Transition is measured 200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested.
5
HM6288 Series
Read Timing Waveform (1)
tRC Address tAA tOH Dout Previous valid data Valid Data tOH
Notes: 1. WE is high for read cycle. 2. Device is continously selected. CS = VIL
Read Timing Waveform (2)
tRC CS tACS Dout tLZ High impedance tPU VCC supply current ICC ISB 50% Valid Data tPD 50% High impedance tHZ
Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with CS transition low.
6
HM6288 Series
Write Cycle
HM6288-25 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Date valid to end of write Data hold time Write enabled to output in high-Z Output active from end of write Note: Symbol t WC t CW t AW t AS t WP t WR t DW t DH t WZ
*1 *1
HM6288-35 Min 35 30 30 0 30 0 20 0 0 5 Max -- -- -- -- -- -- -- -- 10 -- Unit ns ns ns ns ns ns ns ns ns ns
Min 25 20 20 0 20 0 12 0 0 5
Max -- -- -- -- -- -- -- -- 8 --
t OW
1. Transition is measured 200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested.
7
HM6288 Series
Write Timing Waveform (1) (WE Controlled)
tWC Address tCW CS tAW tAS WE tDW Din tWZ *3 Dout Valid Data tOW *4 High impedance tOH *5 tDH *4 tWP *1 tWR *2
Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. 5. If CS is low during this period, I/O pins are in the output state after tOW. Then the data input signals of opposite phase to the outpus must not be applied to them.
8
HM6288 Series
Write Timing Waveform (2) (CS Controlled)
tWC Address tAW tAS tCW CS tWP *1 WE tDW Din Valid Data High impedance *3 Dout tDH tWR *2
Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state.
9
HM6288 Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
Data retention characteristics are guaranteed only for L version.
Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test Conditions CS V CC -0.2 V, Vin V CC -0.2 V or 0 V Vin 0.2 V
Data retention current
I CCDR
-- --
-- -- --
*1
50*2 35 -- --
*3
A A ns ns See retention waveform
Chip deselect to data retention time Operation recovery time Notes: 1. t RC = read cycle time 2. VCC = 3.0 V 3. VCC = 2.0 V
t CDR tR
0 t RC
--
Low V CC Data Retention Waveform
Data retention mode 4.5 V tCDR 2.2 V VDR CS 0V CS VCC - 0.2 V tR
VCC
10
HM6288 Series
Package Dimensions
HM6288P/LP Series (DP-22NB)
27.08 27.90 Max 22 12 6.60 7.00 Max Unit: mm
1 0.88 1.30 Max 1.3
11
2.54 Min 5.08 Max
7.62
0.51 Min
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
HM6288JP/LJP Series (CP-24D)
15.63 16.00 Max 24 13 7.62 0.13 8.64 0.13
Unit: mm
1
0.74
12 3.50 0.26
0.21 2.40 + 0.24 -
1.30 Max
0.43 0.10
1.27 0.10
0.80
+0.25 -0.17
6.76 - 0.16
+ 0.35
11

▲Up To Search▲

Price & Availability of HM6288SERIES

	To Download HM6288SERIES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .